The first functional, and reasonably reliable, random access memory was designed and built by Jay Forrester of MIT as part of the Whirlwind project. In August of 1953, the first bank of storage containing one thousand 16-bit words was wired into the whirlwind. This bank of memory occupied approximately 30 cubic feet. In the thirty years since this epic event, memory designers have exerted unending efforts to reduce the physical size of random access memories. A major breakthrough occurred in the early 1970's with the introduction of reliable MOS dynamic memory devices. Due to their intrinsically small size and extremely low power requirements, a step function improvement occurred in the reduction of memory volume. Today, a memory module of 2 megabyte capacity can be contained in a volume of less than a tenth of cubic foot, a three hundred to one volume reduction and a thousand to one increase in storage capacity.
There are three considerations which motivate the drive for reduced memory size.
1. Reducing the size of any product generally reduces the manufacturing cost. This has been particularly true with random access memories during the transition from core to semiconductor followed by the continued decrease in price of semiconductor devices.
2. The limit to the speed of operation of a random access memory can be limited by the memory's physical size. If the memory system is large, the propagation delays through the memory can limit the overall speed of the computer.
3. Frequently there are product constraints which demand, for the product to be feasible, that a given amount of memory must be contained within a limited physical space. This constraint appears within many military systems and in the commercial world of products such as desk top computers.
One of the fundamental limits on the performance of a computer is the memory access time. This is the time required to transmit a memory address to the memory and receive an item of data from the memory. The von Neumann architecture is ultimately limited in its performance to the speed with which this memory access function can be executed. The access time is made up only in part by the access time of the memory devices themselves. In addition to this access time, there are various times associated with driving the address bus, decoding the address, and driving the data bus back to the processor. The highest theoretical potential for high speed performance is found when the memory device is in juxtaposition to the processor, that is, a single chip microcomputer. In a computer system which has more memory than can be contained on the processor chip, the various propagation delays, which are added to the access time of the memory device, can attain major significance in determining the access time of the memory.
To illustrate the influence of packaging size on performance, let us consider the following hypothetical case. Consider a memory board having an access time of 135 nanoseconds. The memory boards are plugged into a back panel which has a round trip propagation delay of 15 nanoseconds for each card slot. In other words, a computer/memory system which used one memory board, would have a memory access time of 135+15=150 nanoseconds. The access time of a two board memory system would be 165 nanoseconds, etc. The system we are describing is synchronous and has a clock period of 60 nanoseconds. The maximum number of boards which can be plugged into the system and maintain a three clock period for a memory access will be shown in the equation below: EQU N&gt;=((60.times.3)-135)/15,
where N is an integer, thus EQU N=3.
If the memory boards in question have a capacity of 2 megabytes, then the maximum memory size for this system is 6 megabytes. We will assume that the fundamental execution cycle of the computer using this memory is also three clocks or 180 nanoseconds. In other words, a new memory request could be issued every three clocks.
If we wish to increase the maximum capacity of this computer by a factor of four, the number of boards would grow from three to twelve. The access time of a twelve board system would be 315 nanoseconds. However, as our clock period is 60 nanoseconds, a five clock memory access would not be long enough, therefore, six clocks are required. By quadrupling the amount of memory, we will have cut the performance of the computer system in half. The obvious answer to maintaining the performance of a computer then is to continue to increase the intrinsic density of memory so that a memory of the desired size can be constructed which will have an access time of less than the access time desired by the processor itself. In other words, in this example, a four fold increase of density in the memory would have maintained a three clock period and thus, would have maintained the performance of the system.